1. Introduction

Recordings of the neural Electroencephalogram (EEG) signals from many locations of the brain are an important source of the information for studying the function of the brain and various neurological disorders [1,2]. Therefore, multichannel Electroencephalogram (EEG) seizure detection SoCs are widely adopted in medical practice and in research [3,4], but most of them have an obvious limitation-limited number (no more than 8) of channels, whereas the American Clinical Neurophysiology Association sets the minimum technical standard recommendation for pediatric EEG as16 channels with bipolar and referential montages [4].

These recordings occupy a frequency band of from 1 Hz to about 40 Hz and have the small amplitudes ranging from 0.5 μVp to 100 μVp [5]. Due to the small amplitudes, EEG signals need to be amplified before digitization. Thus, the Low-Noise Amplifiers (LNA) are needed in an EEG signal recording sensor. Usually, the input-referred noise of the LNAs should be less than 4 μVrms [6]. EEG monitoring is one application where designers have targeted microvolt even sub-microvolt input-referred noise over a designed signal band [5]. For low-bandwidth and low-noise applications, the front-end amplifier of the recording sensor presents a power-consumption bottleneck since its current draw is noise-limited and cannot be scaled with the low data-rate [7]. Therefore, the prior works to improve the energy-efficiency of LNAs includes chopper [8], inverter-based LNAs [7], and low-supply-voltage amplifier design reaching 1.2 V [1,6]. However, most of LNAs still struggles on the aspect of energy efficiency and power consumption.

Therefore, to further improve the energy-efficiency, this paper uses a low supply of 0.7 V to design a 16-channel EEG analog front end. Our Subthreshold Symmetrical LNA (SSLNA) decreases the power dissipation and maintains the other aspects comparable, via scaling the supply voltage to 0.7 V and keeping all the transistors operate in the subthreshold region. This paper is organized as follows. The topologies and analysis of the whole analog front end, the proposed SSLNA and the other circuits are presented in Section II. The results are stated in Section III. Finally, the conclusions are given in Section IV.

2. Topology

1. Analog Front End Topology

The whole analog front-end topology is shown in Figure 1. It consists of the proposed sampling and processing amplifiers for 16 channels, a 16:1 multiplexer, an 8-bit modified flash ADC, a CMOS reference and a clock tree. The EEG signals are filtered by High-Pass Filters (HPF) and then processed by proposed SSLNAs. Then, the corresponding channel is chosen by one multiplexer to transfer one SSLNA output to a modified flash ADC. Then the flash ADC converts the analog signal to digital signals. Moreover, the CMOS reference provides the bias current and voltage.

2. Proposed Subthreshold Symmetrical LNA

As shown in Figure 2a each channel has one HPF and one closed-loop SSLNA It’s easy to obtain the transfer function GHPF of HPF and the gain Again of closed-loop SSLNA as the followings

where R3 is the filter resistor, C1 is the filter capacitor, and R1 and R2 are the gain resistors. Noting that, the high pass frequency and closed-loop gain should respectively be around 0.3 Hz and around 40 dB for EEG signals.

Figure 2b shows the SSLNA. The SSLNA is based on a common symmetrical OTA but works at a low supply of 0.7V. It consists of one differential pairs implemented by the transistors M1 and M2, three pairs of current mirrors M3-M5, M4-M6 and M7-M8, a bias current M9, as well as the miller compensation C1 and R1 keeping the SSLNA stable.

Due to the transistors working in the subthreshold region, the drain current of the transistors should be

where ID0, W, L, Vgs, Vds, q, a, kB and T are the basic drain current, channel width, channel length, gate-source voltage and drain-source voltage, electron charge, the ration of the sum of oxide and depletion capacitances to oxide capacitance, Boltzmann constant and temperature, respectively. ID0 and a can be expressed as

where COX, Cdepl, μ and Vth are the oxide capacitance per unit area, depletion capacitance, carrier mobility and the threshold voltage, respectively.

According to the OTA principle, the gain and bandwidth can be easily written as

where COUT is the capacitance of node OUT, roN (roP) is the equivalent resistance of M8 (M6) and gmg is the transconductor of M1 or M2. The transconductor gmg and the equivalent resistance ro can be calculated as

Therefore, via substituting gmg and ro into and bandwidth BW, it’s easy to find the following

Noting that, the target of the bandwidth i.e. a low pass frequency is around 500 Hz for EEG signal.

Due to all the transistors operating in the subthreshold region reduce the ultra-low power, and hence the root mean square (rms) voltage of the input mosfet at the frequency band of from f1 to f2 is express as [9]

3. Flash ADC

A N-bit modified Flash ADC is achieved combining Threshold Inverter Quantization (TIQ) and multiplexer-based decoder. TIQ based on a single NMOS comparator (consisting of a resistor and CMOS inverters) is transplanted to overcome the drawbacks of traditional comparator and TIQ based on two cascaded CMOS inverters. Traditional comparator requires a large number of transistors causing the big chip area and power consumption. TIQ based on two cascaded CMOS inverters requires its WL ratios being increased up to maybe thousand times when the number of bits is increased. The chosen TIQ based on a single NMOS comparator is shown in Figure 3a [10]. The resistor is used to set the voltage between source and bulk Vsb, the first inverter is used to compare the input VIN and threshold voltage VTH, and the second inverter is used to amend the comparison result. VTH of NMOS can be expressed as

where VTH0 is threshold voltage when source and bulk is connected, VTH0 is body effect parameter, φf is semiconductor parameter. So Vs can be biased and adjusted by the series resistors to attain reference voltage. The NMOS operating mechanism depended on the relationship of Vgs and VTH. If Vgs<VTH, NMOS is at the “cut-off” region, there is no current flowing through NMOS and it will output a negative logic “0”. Otherwise, NMOS is at the “ON” region (whether in non-saturation or saturation), Vout=Vs+ID∙RMOS and it will output a positive logic “1”. Obviously, WL ratio of NMOS transistor need be chosen to make a good trade-off between input range and area, thus we use 5 μm0.5 μm.

Multiplexer based decoder is used to overcome the disadvantages of ROM, Wallace tree and folded decoders. ROM decoder is slow and power consuming. Wallace tree decoder and folded decoder require a larger length of critical path which is approximately third and twice of multiplexer-based decoder, respectively. The used multiplexer-based decoder is shown in Figure 3b. For an N-bit flash ADC, the Most Significant Bit (MSB) of the binary outputs is high if more than half of the outputs in the thermometer scale are logic one. Hence MSB is A2N-1. To find the second most significant bit (MSB-1) of the original thermometer scale is divided into two partial thermometer scales, separated by A2N-1. The partial thermometer scale to decode is chosen by a set of 2:1 multiplexers, where the previous decoded binary outputs are connected to the control input of the multiplexers. MSB-1 is then found from the chosen partial thermometer scale in the same way as MSB was found from the full thermometer scale. Similarly, all the N bits can be obtained. In general, the decoder requires 2:1 multiplexers with a number of yN=q=1N-1(2N-q-1), and the critical path in units of tMUX is N-1.

Usually, the signal-to-noise rate (SNR) of ADC is defined as

where vin_noise_ADC is the peak value of ADC input noise, vin_noise_ADC is the rms value of ADC input noise, RADC is the total resistance of ADC and VADC_range is the input range of ADC which is around 0.5V. Therefore, using the targets in last subsection, it is estimated that SNR≈49.63dB.

Besides, the relationship of SNR and ADC accuracy N can be express as

SNR=6.02N+1.76

Thus, to make SNR≥49.63dB, the modified flash ADC requires its accuracy meeting N≥7.952. Therefore, our flash ADC has 8 bits.

4. CMOS Reference

This paper transplants a CMOS reference structure [12,13] shown in Figure 4 to 0.13μm CMOS process. A self-biasing circuit (M1, M2, M3 and M4) and MOS resistor M5 generates the reference current Ip. The transistor M7 and two source-coupled pairs (M6 and M9, M8 and M10) generates the reference voltage VREF. Via adjusting the aspect ratios of the transistors, the zero TC principle of CMOS reference is derived as

VREF=VTH0+C

where C is a parameter which is dependent on process, but not on the temperature. More details can be seen in Refs. [12, 13].

5. Clock Tree

The ring oscillator, which uses an odd number of inverters to give the effect of a single inverting amplifier with a gain of greater than one, is used as the basic clock generator. If tINV represents the time-delay of a single inverter and nINV  represents the number of inverters, the frequency is given by fclock=12∙tINV∙nINV. Then a series of D flip flops are used as the even frequency dividers. Number of inverters is chosen as three to reduce area, power consummation and design complexity. Thus, the clock tree is obtained as shown in Figure 5.

3. Results and Comparisons

1. Simulation Results

Figure 6 shows the frequency response of one channel with HPF and closed-loop SSLNA. It can be seen that it has a low-frequency gain of about 38 dB, a bandwidth of about 0.25~480 Hz and a phase margin of about 61˚.

The noise spectrum from 0.1 Hz to 100 kHz is shown in Figure 7. The Input-Referred Noise Voltages (IRNV) in the range of 0.1~480Hz are about 2.23 μVrms/Hz and the corner frequency is about 300 Hz. The Noise Efficiency Factor (NEF) is calculated as 4.85. Obviously, the gain, bandwidth and noise voltage meet the targets set for EEG signals in Sec. II. That is to say, even at a low supply of 0.7V increasing the total widths of all the transistors and adjusting the ratios of width to length can achieve the low noise, meanwhile, maintain appropriate gain and bandwidth.

A sinusoidal signal with a frequency of 10 Hz and an amplitude of 1 mV is sent to SSLNA configured as unit gain. It can be seen from Figure 8 that the Dynamic Range (DR) between the fundamental frequency and 3rd harmonic is 90 dB and the Total Harmonic Distortion (THD) is 0.25%.

The slew rate is bigger than 2500 V/s as shown in Figure 9.

From Figure 10 the output swing is from 0.1 V to 0.65 V and the Input Common Mode Range (ICMR) is from 0.09 V to 0.65 V.

As shown in (Figure 11), SSLNA under closed-loop has a Common-Mode Rejection Ratio (CMRR) of about 78 dB and a power-supply rejection ratio (PSRR) of about 71 dB, which are sufficient for EEG signals.

Figure 12 and Figure 13 respectively show the power loss and layout graph of the analog front end implemented in a 0.13μm CMOS technology. On the aspect of power loss, the analog front end has a total loss of 12.65 μW including 214 nW from one SSLNA. On the aspect of layout area, it has a total dimension of 7.3×3 mm2 including 1.6×0.4 mm2 from one SSLNA, 0.5×0.26 mm2 from one ADC and 0.13×0.26 mm2 from the CMOS reference. To decrease the offset of SSLNA caused by fluctuation of ion density, each transistor is decomposed into even centrosymmetric transistors with half ratio.

2. Comparisons

BW, IRNV, NEF, THD, DR, SR, ICMR, CMRR and PSRR is bandwidth, input referred noise voltage, noise efficiency factor, total harmonic distortion, dynamic range, slew rate, input common mode range, common mode rejection ratio and power supply rejection ratio. The comparisons of the proposed SSLNA with recent LNAs are listed in Table 1. The SSLNA makes the supply voltage and power dissipation respectively smaller than 1 V and 250 nW, and also achieves the comparable other parameters with those of recent works. The bandwidth is 0.25~480 Hz is enough for the EEG recordings.

4. Conclusion

This work presented a successful design and validation of a Subthreshold Symmetrical Low Noise Amplifier (SSLNA) of 16-channel analog front end for electroencephalogram signals in a 0.13 μm CMOS process. The SSLNA features a low supply voltage of 0.7 V, a low power dissipation of 214 nW, a direct current gain of about 38 dB and a bandwidth of 0.25~480 Hz. Besides, the input-referred noise voltage is 2.23 μVrms and the noise efficiency factor is 4.85. Moreover, the SSLNA has a dynamic range of 90 dB and a total harmonic distortion of 0.25% for a sinusoidal input with the frequency of 10 Hz and the amplitude of 1 mV. Besides, CMRR and PSRR respectively are 78 dB and 71 dB.

5. Acknowledgment

This project is sponsored by the corporate gift donations to the VLSI Design Center at Duke ECE Department under Dr. James Morizio’s direction and the China Scholarship Council under grant no. 201506280038.

Figure 1: Analog front end topology.

(a)

(b)

Figures 2(a,b): Closed-loop SSLNA, (b) subthreshold symmetrical LNA.

Figures 3(a,b): TIQ with a single MOS comparator, (b) multiplexer based decoder.

Figure 4:CMOS reference.

Figure 5: Clock tree.

Figure 6: Frequency response.

Figure 7: Noise spectrum.

Figure8: Dynamic range and THD.

Figure 9: Slew rate.

Figure 10: Output swing and input common mode range.

Figure11: CMRR and PSRR.

Figure12: Power loss.

Figure13: Layout.

Table 1: Comparisons of SSLNA with recent LNAs.

1.       Bagheri A, Salam MT, Velazquez JLP, Genov R (2016) Low-Frequency Noise and Offset Rejection in DC-Coupled Neural Amplifiers: A Review and Digitally-Assisted Design Tutorial. IEEE Transactions on Biomedical Circuits and Systems 11: 161-176.

2.       Yoo J, Yan L, El-Damak D, Altaf MAB, Shoeb AH, Chandrakasan AP (2013) An 8-channel scalable EEG acquisition SoC with patient-specific seizure classification and recording processor. IEEE Journal of Solid-State Circuits 48: 214-228.

3.       Kim J, Kim DS, Kim C (2013) A Single-Inductor Eight-Channel Output DC-DC Converter with Time-Limited Power Distribution Control and Single Shared Hysteresis Comparator. IEEE Transactions on Circuits and Systems I: Regular Papers 60: 3354-3367.

4.       Altaf MAB, Zhang C, Yoo J (2015) A 16-channel patient-specific seizure onset and termination detection soc with impedance-adaptive transcranial electrical stimulator. IEEE Journal of Solid-State Circuits 50: 2728-2740.

5.       Cota OF,Plachta D, Stieglitz T, Manoli Y, Kuhl M (2015) In-vivo characterization of a 0.8-3 µV RMS input-noise versatile CMOS pre-amplifier. in 2015 7^th International IEEE/EMBS Conference on Neural Engineering (NER) 2015: 458-546.

6.       ChandrakumarH, Marković (2015) A Simple Area-Efficient Ripple-Rejection Technique for Chopped Biosignal Amplifiers. IEEE Transactions on Circuits and Systems II: Express Briefs 62: 189-193.

7.       YaulFM, Chandrakasan AP (2016) A sub-μW 36nV/√ Hz chopper amplifier for sensors using a noise-efficient inverter-based 0.2 V-supply input stage. in 2016 IEEE International Solid-State Circuits Conference (ISSCC) 2016: 94-95.

8.       Maruyama M, Taguchi S, Yamanoue M, Iizuka K (2016) An Analog Front-End for a Multifunction Sensor Employing a Weak-Inversion Biasing Technique With 26 nVrms, 25 aCrms, and 19 fArms Input-Referred Noise. IEEE Journal of Solid-State Circuits 51: 2252-2261.

9.       Arnaud A, Montoro CG (2004) Consistent noise models for analysis and design of CMOS circuits. IEEE Transactions on Circuits and Systems I: Regular Papers 51: 1909-1915.

10.    Steyaert MSJ, Sansen WMC, Zhongyuan C (1987) A micropower low-noise monolithic instrumentation amplifier for medical purposes. IEEE Journal of Solid-State Circuits22: 1163-1168.

11.    Hsieh YY, Lin ZM (2011) An 8-bit 1.42 GS/s 0.54 mW CMOS Flash ADC. in Information, Communications and signal Processing (ICICS) 2011 8^th International Conference on 2011: 1-4.

12.    Wang C, Li Z, Zhao K, Guo Q (2016) Efficient Self-Powered Convertor with Digitally Controlled Oscillator-based Adaptive Maximum Power Point Tracking and RF Kick-start for Ultralow-voltage Thermoelectric Energy Harvesting. IET Circuits, Devices & Systems 10: 147-155.

13.    Ueno K, Hirose T, Asai T, Amemiya Y (2009) A 300 nW, 15 ppm/ C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs. IEEE Journal of Solid-State Circuits44: 2047-2054.

14.    Wang TY, Lai MR,Twigg CM, Peng SY (2014) A fully reconfigurable low-noise biopotential sensing amplifier with 1.96 noise efficiency factor. IEEE transactions on biomedical circuits and systems8: 411-422.

15.    CorradiF, Indiveri G (2015) A neuromorphic event-based neural recording system for smart brain-machine-interfaces. IEEE Transactions on Biomedical Circuits and Systems9: 699-709.